SMJ320F240 Datasheet, PDF (48/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
watchdog (WD) and real-time interrupt (RTI) module (continued)
Any
Write
RTICNTR.7 – 0
CLR
8-Bit
Real-Time
Counter
/16384
/2048
/512
CLR
/256
16-kHz
WDCLK
System
Reset
/128
7-Bit
Free-
/64
Running /32
Counter _/16
/8
/4
CLR
/2
WDCR.2 – 0
210
WDPS
000
001
010
011
100
101
110
111
WDCR.6
WDDIS
111
110
101
100
011
010
001
000
RTICR.2 – 0
210
RTIPS
RTICR.6
RTI ENA
DQ
CLR
INT Request
(Level 1 Only)
INT Acknowledge
RTICR.7 _Clear
RTI FLAG RTI Flag
DQ
CLR
RTICR.7 Read
RTI FLAG ^{RTI Flag}
RTICR.7
RTI FLAG
Clear
RTI Flag
WDCNTR.7 – 0
8-Bit Watchdog
Counter
CLR
One-Cycle
Delay
PS/257
WD FLAG
WDCR.7
Reset Flag
WDKEY.7 – 0
Watchdog
Reset Key
Register
Bad Key
55 + AA
Detector
Good Key
WDCHK2–0
WDCR.5 – 3†
3
System Reset
3
101
(Constant
Value)
† _{Writing to bits WDCR.5 – 3 with anything but the correct pattern (101) generates a system reset.}
Figure 15. WD / RTI Module Block Diagram
System
Reset
Request
Bad WDCR Key
48
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