SMJ320F240 Datasheet, PDF (25/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
external interrupts (continued)
Table 8 is a summary of the external interrupt capability of the ’F240.
SGUS029 – APRIL 1999
EXTERNAL
INTERRUPT
XINT1
NMI
XINT2
XINT3
PDPINT
CONTROL
REGISTER
NAME
XINT1CR
NMICR
XINT2CR
XINT3CR
EVIMRA
Table 8. External Interrupt Types and Functions
CONTROL
REGISTER
ADDRESS
INTERRUPT
TYPE
CAN DO
NMI?
DIGITAL
I/O PIN
7070h
A
No
Input only
7072h
A
Yes
Input only
7078h
C
No
I/O
707Ah
C
No
I/O
742Ch
N/A
N/A
N/A
MASKABLE?
Yes
(Level 1 or 6)
No
Yes
(Level 1 or 6)
Yes
(Level 1 or 6)
Yes
(Level 2)
clock generation
The SMJ320F240 has an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The only external component necessary for
this module is an external fundamental crystal, or oscillator.
The PLL-based clock module provides two basic modes of operation: oscillator mode and clock-in mode.
D oscillator mode
This mode allows the use of a 4-, 6-, or 8-MHz external reference crystal to provide the time base to the
device. The internal oscillator circuitry is initialized by software to select the desired CPUCLK frequency,
which can be the input clock frequency, the input clock frequency divided by 2 (default), or a clock frequency
determined by the PLL.
D Clock-in mode
This mode allows the internal crystal oscillator circuitry to be bypassed. The device clocks are generated
from an external clock source input on the XTAL1/CLKIN pin. The device can be configured by software
to operate on the input clock frequency, the input clock frequency divided by 2, or a clock frequency
determined by the PLL.
The ’F240 runs on two clock frequencies: the CPU clock (CPUCLK) frequency, and the system clock (SYSCLK)
frequency. The CPU, memories, external memory interface, and event manager run at the CPUCLK frequency.
All other peripherals run at the SYSCLK frequency. The CPUCLK runs at 2x or 4x the frequency of the SYSCLK;
for example, for 2x, CPUCLK = 20 MHz and SYSCLK = 10 MHz. There is also a clock for the watchdog timer,
WDCLK. This clock has a nominal frequency of 16384 Hz (214 Hz) when XTAL1/CLKIN is a power of two or
a sum of two powers of two; for example, 4194304 Hz (222 Hz), 6291456 (222 + 221 Hz), or 8388608 Hz
(223 Hz).
The clock module includes three external pins:
1. XTAL1/CLKIN clock source/crystal input
2. XTAL2
output to crystal
3. OSCBYP
oscillator bypass
For the external pins, if OSCBYP ≥ V_IH, then the oscillator is enabled and if OSCBYP ≤ V_IL, then the oscillator
is bypassed and the device is in clock-in mode. In clock-in mode, an external TTL clock must be applied to the
XTAL1/CLKIN pin. The XTAL2 pin can be left unconnected.
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