SMJ320F240 Datasheet, PDF (8/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
CVSS
8
3
14
20
29
46
VSS
59
61
71
92
104
113
120
TYPE†
DESCRIPTION
SUPPLY SIGNALS
I
Digital core logic ground reference
I
Digital logic ground reference
VSSA
87
2
13
21
DVDD
47
(See Note 1)
62
93
103
121
I
Analog ground reference
I
Digital I/O logic supply voltage
CVDD
7
(See Note 1)
60
I
Digital core logic supply voltage
VCCA
VREFHI
VREFLO
84
I
Analog supply voltage
85
I
ADC analog voltage reference high
86
I
ADC analog voltage reference low
TEST SIGNALS
TCK
IEEE standard test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
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I
on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction
register, or selected test data register of the ’C2xx core on the rising edge of TCK. Changes at the TAP
output signal (TDO) occur on the falling edge of TCK.
TDI
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I
IEEE standard test data input (TDI). TDI is clocked into the selected register (instruction or data) on a
rising edge of TCK.
TDO
IEEE standard test data output (TDO). The contents of the selected register (instruction or data) are
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O/Z shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state when OFF is active
low.
TMS
33
I
IEEE standard test mode select. This serial control input is clocked into the TAP controller on the rising
edge of TCK.
† _{I = input, O = output, Z = high impedance}
NOTE 1: VDDreferstosupplyvoltagetypesCVDD(digitalcoresupplyvoltage),DVDD(digitalI/Osupplyvoltage),andVDDP(programmingvoltage
supply). All voltages are measured with respect to VSS.
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