SMJ320F240 Datasheet, PDF (73/99 Pages) Texas Instruments – DSP CONTROLLER

RS and PORESET timings (continued)
PORESET
tw(RSL)
tw(RSL1)
RS†
SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
A0–A15
td(RS)
0000h
td(EX)
0001h
† _{RS is driven low by any device reset, which includes asserting PORESET, RS, access to an illegal address, execution of a software}
reset, or a watchdog timer reset.
Figure 31. Power-On Reset Timings
XF, BIO, and MP/MC timings
switching characteristics over recommended operating conditions (see Figure 32)
td(XF)
PARAMETER
Delay time, CLKOUT high to XF high/low
MIN MAX UNIT
11 ns
timing requirements, H = 0.5t_c(CO) (see Figure 32)
MIN MAX UNIT
tw(BIOL)
Pulse duration, BIO low
2H + 16
ns
tw(MPMCV)
Pulse duration, MP/MC valid†
2H + 24
ns
† _{This is the minimum time the MP/MC pin needs to be stable in order to be recognized by internal logic; however, for proper operation, the user}
must maintain a valid level for the duration of the entire memory access (or accesses) on- or off-chip.
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