SMJ320F240 Datasheet, PDF (7/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
Terminal Functions (Continued)
SGUS029 – APRIL 1999
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS
SPISIMO/IO
45
I/O
SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPISOMI/IO
48
I/O
SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPICLK/IO
49
I/O
SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device
resets.
SPISTE/IO
51
I/O
SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pin is configured
as a digital input by all device resets.
COMPARE SIGNALS
PWM1/CMP1
PWM2/CMP2
PWM3/CMP3
PWM4/CMP4
PWM5/CMP5
PWM6/CMP6
94
95
96
97
98
Compare units compare or PWM outputs. The state of these pins is determined by the
O/Z compare/PWM and the full action control register (ACTR). CMP1 – CMP6 go to the
high-impedance state when unmasked PDPINT goes active low, and when reset (RS) is asserted.
99
INTERRUPT AND MISCELLANEOUS SIGNALS
Reset input. RS causes the SMJ320F240 to terminate execution and sets PC = 0. When RS is
RS
35
I/O
brought to a high level, execution begins at location zero of program memory. RS affects (or sets
to zero) various registers and status bits. In addition, RS is a bidirectional (open-drain output) pin.
If RS is left undriven, then a 20-Ω pull-up resistor should be used.
MP/MC
37
I
MP/MC (microprocessor/microcomputer) select. If MP/MC is low, internal program memory is
selected. If it is high, external program memory is selected.
NMI
40
I
Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state
of the INTM bit of the status register. NMI has programmable polarity.
PORESET
Power-on reset. PORESET causes the SMJ320F240 to terminate execution and sets PC = 0.
41
I
When PORESET is brought to a high level, execution begins at location zero of program memory.
PORESET affects (or sets to zero) the same registers and status bits as RS. In addition,
PORESET initializes the PLL control registers.
XINT1
53
I
External user interrupt no. 1
XINT2/IO
54
I/O
External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
XINT3/IO
55
I/O
External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
PDPINT
Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low, the
52
I
timer compare outputs immediately go to the high-impedance state.
CLOCK SIGNALS
XTAL2
57
O
XTAL1/CLKIN
58
I/Z
OSCBYP
56
I
† _{I = input, O = output, Z = high impedance}
PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL
mode (CLKMD[1:0] = 1x, CKCR0.7 – 6). This pin can be left unconnected in oscillator bypass
mode (OSCBYP ≤ VIL). This pin goes in the high-impedance state when EMU1/OFF is active low.
PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode
(CLKMD[1:0] = 1x, CKCR0.7 – 6), or is connected to an external clock source in oscillator bypass
mode (OSCBYP ≤ VIL).
Bypass oscillator if low
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