SMJ320F240 Datasheet, PDF (55/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
instruction set summary (continued)
Table 14. SMJ320F240 Instruction Set Summary (Continued)
’F240
MNEMONIC
POP
POPD
PSHD
PUSH
RET
RETC
ROL
ROR
RPT
SACH
SACL
SAR
SBRK
SETC
SFL
SFR
SPAC
SPH
SPL
SPM
SQRA
SQRS
SST
DESCRIPTION
Pop top of stack to low accumulator
Pop top of stack to data memory
Push data-memory value onto stack
Push low accumulator onto stack
Return from subroutine
Conditional return from subroutine
Rotate accumulator left
Rotate accumulator right
Repeat instruction as specified by data-memory value
Repeat instruction as specified by immediate value
Store high accumulator with shift
Store low accumulator with shift
Store auxiliary register
Subtract from auxiliary register short immediate
Set carry bit
Configure block as program memory
Disable interrupt
Set overflow mode
Set test / control flag
Set external flag XF
Set sign-extension mode
Shift accumulator left
Shift accumulator right
Subtract P register from accumulator
Store high-P register
Store low-P register
Set P register output shift mode
Square and accumulate
Square and subtract previous product from accumulator
Store status register ST0
Store status register ST1
SPLK
Store long immediate to data memory
SUB
Subtract from accumulator long immediate with shift
Subtract from accumulator with shift
Subtract from high accumulator
Subtract from accumulator short immediate
WORDS/
CYCLES
1/1
1/1
1/1
1/1
1/4
1/4/2
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
2/2
2/2
1/1
1/1
1/1
MSB
1011
1000
0111
1011
1110
1110
1011
1011
0000
1011
1001
1001
1000
0111
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1000
1000
1011
0101
0101
1000
1000
1010
1011
0011
0110
1011
OPCODE
LSB
1110 0011 0010
1010 IADD RESS
0110 IADD RESS
1110 0011 1100
1111 0000 0000
11TP ZLVC ZLVC
1110 0000 1100
1110 0000 1101
1011 IADD RESS
1011 KKKK KKKK
1SHF IADD RESS
0SHF IADD RESS
0ARx IADD RESS
1100 KKKK KKKK
1110 0100 1111
1110 0100 0101
1110 0100 0001
1110 0100 0011
1110 0100 1011
1110 0100 1101
1110 0100 0111
1110 0000 1001
1110 0000 1010
1110 0000 0101
1101 IADD RESS
1100 IADD RESS
1111 IADD RESS
0010 IADD RESS
0011 IADD RESS
1110 IADD RESS
1111 IADD RESS
1110 IADD RESS
16-Bit Constant
1111 1010 SHFT
16-Bit Constant
SHFT IADD RESS
0101 IADD RESS
1010 KKKK KKKK
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