SMJ320F240 Datasheet, PDF (17/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
device reset and interrupts (continued)
D Software-generated interrupts for the ’F240 device include:
– The INTR instruction. This instruction allows initialization of any ’F240 interrupt with software. Its
operand indicates to which interrupt vector location the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
– The NMI instruction. This instruction forces a branch to interrupt vector location 24h, the same location
used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI pin low or by
executing an NMI instruction. This instruction globally disables maskable interrupts.
– The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
– An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
reset
The reset operation ensures an orderly startup sequence for the device. There are five possible causes of a
reset, as shown in Figure 4. Three of these causes are internally generated; the other two causes, the RS and
PORESET pins, are controlled externally.
To Device
Watchdog Timer Reset
Software-Generated Reset
Illegal Address Reset
Reset (RS) Pin Active
Power-On Reset (PORESET) Pin
Active
Reset
Signal
Figure 4. Reset Signals
To Reset Out
The five possible reset signals are generated as follows:
D Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an
improper value is written to either the watchdog key register or the watchdog control register. (Note that
when the device is powered on, the watchdog timer is automatically active.)
D Software-generated reset. This is implemented with the system control register (SYSCR). Clearing the
RESET0 bit (bit 14) or setting the RESET1 bit (bit 15) causes a system reset.
D Illegal address reset. The system and peripheral module control register frame address map contains
unimplemented address locations in the ranges labeled illegal. Any access to an address located in the
Illegal ranges generate an illegal-address reset.
D Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of as little
as a few nanoseconds is usually effective; however, pulses of one SYSCLK cycle are necessary to ensure
that the device recognizes the reset signal.
D Power-on reset pin active. To generate a power-on reset pulse on the PORESET pin, a low-level pulse
of one SYSCLK cycle is necessary to ensure that the device recognizes the reset signal.
Once a reset source is activated, the external RS pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the SMJ320F240 device to reset external system components. Additionally, if a brown-out
condition (V_CC < V_CCmin for several microseconds causing PORESET to go low) occurs or the RS pin is held
low, then the reset logic holds the device in a reset state for as long as these actions are active.
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