SMJ320F240 Datasheet, PDF (68/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
memory and parallel I/O interface write timings
switching characteristics over recommended operating conditions for a memory write
H = 0.5t_c(CO)† (see Figure 27)
PARAMETER
MIN
MAX
td(CO-A)W
Delay time, CLKOUT/IOPC1 high to address valid
17
td(CO-D)
Delay time, CLKOUT/IOPC1 low to data bus driven
15
td(D-WH)
Delay time, address valid after WE high
H–8
tw(WH)
tw(WL)
td(CO-WL)
Pulse duration, WE high
Pulse duration, WE low
Delay time, CLKOUT/IOPC1 low to WE low
2H – 11
2H – 11
9
td(CO-WH)
Delay time, CLKOUT/IOPC1 low to WE high
9
td(WH-D)
Delay time, write data valid before WE high
2H – 8
td(D-WHZ)
Delay time, WE high to data bus Hi-Z
0
5
td(CO-SL)W
Delay time, CLKOUT/IOPC1 low to STRB low
10
td(CO-SH)W
Delay time, CLKOUT/IOPC1 low to STRB high
6
td(CO-ACTL)W Delay time, CLKOUT/IOPC1 high to PS, DS, IS, and BR low
10
td(CO-ACTH)W Delay time, CLKOUT/IOPC1 high to PS, DS, IS, and BR high
10
td(CO-RWL)
Delay time, CLKOUT/IOPC1 high to R/W low
10
td(CO-RWH)
Delay time, CLKOUT/IOPC1 high to R/W high
10
† _{All timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output.}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
68
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