SMJ320F240 Datasheet, PDF (38/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
external memory interface (continued)
The SMJ320F240 supports zero-wait-state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the ’F240 to buffer the transition of the data bus from input to output (or output
to input) by a half cycle. In most systems, SMJ320F240 ratio of reads to writes is significantly large to minimize
the overhead of the extra cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using the ready signal or using the software wait-state
generator. Ready can be used to generate any number of wait states.
event-manager (EV) module
The event-manager module includes general-purpose (GP) timers, full compare units, capture units, and
quadrature-encoder pulse (QEP) circuits. Figure 11 shows the functions of the event manager.
general-purpose (GP) timers
There are three GP timers on the SMJ320F240. The GP timer x (for x = 1, 2, 3) includes:
D A 16-bit timer up-, up/down-counter, TxCNT for reads or writes
D A 16-bit timer-compare register (double-buffered with shadow register), TxCMPR for reads or writes
D A 16-bit timer-period register (double-buffered with shadow register), TxPR for reads or writes
D A 16-bit timer-control register,TxCON for reads or writes
D Selectable internal or external input clocks
D A programmable prescalar for internal or external clock inputs
D Control and interrupt logic for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
D A timer-compare output pin with configurable active-low and active-high states, as well as forced-low and
forced-high states.
D A selectable direction (TMRDIR) input pin (to count up or down when directional up- / down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. A 32-bit GP timer also can be
configured using GP timer 2 and 3. The compare register associated with each GP timer can be used for
compare function and PWM-waveform generation. There are two single and three continuous modes of
operation for each GP timer in up- or up / down-counting operations. Internal or external input clocks with
programmable prescaler is used for each GP timer. The state of each GP timer/compare output is configurable
by the general-purpose timer-control register (GPTCON). GP timers also provide the time base for the other
event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 1 or 2 for the simple
compares to generate additional compare or PWMs, GP timer 2 or 3 for the capture units and the
quadrature-pulse counting operations.
Double buffering of the period and compare registers allows programmable change of the timer (PWM) period
and the compare/PWM pulse width as needed.
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