SMJ320F240 Datasheet, PDF (24/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
hardware-generated interrupts (continued)
Table 7. ’F240 Interrupt Locations and Priorities (Continued)
INTERRUPT
NAME
OVERALL
PRIORITY
DSP-CORE
INTERRUPT,
AND
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
PERIPHERAL
VECTOR
ADDRESS
OFFSET
MASKABLE?
’F240
SOURCE
PERIPHERAL
MODULE
FUNCTION
INTERRUPT
SPIINT
34
INT5
0005h
Y
SYSIVR
RXINT
35
(701Eh)
0006h
Y
000Ah
TXINT
(System)
36
0007h
Y
SPI
Low-priority SPI interrupt
SCI
SCI receiver interrupt
(low priority)
SCI
SCI transmitter interrupt
(low priority)
ADCINT
37
INT6
SYSIVR
0004h
Y
ADC
Analog-to-digital interrupt
XINT1
XINT2
XINT3
38
39
40
000Ch
(System)
(701Eh)
0001h
0011h
001Fh
Y
Y
Y
External
pins
Low-priority external
user interrupts
RESERVED
41
000Eh
N/A
Y
DSP Core Used for analysis
TRAP
N/A
0022h
N/A
N/A
TRAP instruction vector
external interrupts
The ’F240 has five external interrupts. These interrupts include:
D XINT1. Type A interrupt. The XINT1 control register (at 7070h) provides control and status for this interrupt.
XINT1 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose input pin. XINT1 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
D NMI. Type A interrupt. The NMI control register (at 7072h) provides control and status for this interrupt. NMI
is a nonmaskable external interrupt or a general-purpose input pin. NMI can also be programmed to trigger
an interrupt on either the rising or the falling edge.
D XINT2. Type C interrupt. The XINT2 control register (at 7078h) provides control and status for this interrupt.
XINT2 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a
general-purpose I/O pin. XINT2 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
D XINT3. Type C interrupt. The XINT3 control register (at 707Ah) provides control and status for this interrupt.
XINT3 can be used as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a
general-purpose I/O pin. XINT3 can also be programmed to trigger an interrupt on either the rising or the
falling edge.
D PDPINT. This interrupt is provided for safe operation of the power converter and motor drive. This maskable
interrupt can put the timers and PWM output pins in the high-impedance state and inform the CPU in case
of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. PDPINT is
a Level 2 interrupt.
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