SMJ320F240 Datasheet, PDF (72/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
RS and PORESET timings
switching characteristics over recommended operating conditions for a reset, H = 0.5t_c(CO)
(see Figure 30 and Figure 31)
PARAMETER
tw(RSL1)
Pulse duration, RS low†
td(RS)
Delay time, RS low to program address at reset vector
td(EX)
Delay time, RS high to reset vector executed
† _{The parameter tw(RSL1) refers to the time RS is an output.}
MIN
8tc(SYS)
4H
32H
MAX
UNIT
ns
ns
ns
timing requirements for reset (see Figure 30 and Figure 31)
tw(RSL)
Pulse duration, RS or PORESET low‡
‡ _{The parameter tw(RSL) refers to the time RS is an input.}
MIN MAX
5
UNIT
ns
VCC
XTAL1/CLKIN
PORESET†
RS‡
† _{PORESET is required to be driven low during power up to ensure all clock/PLL registers are reset to a known state.}
‡ _{RS is a bidirectional (open-drain output) pin and can be optionally pulled low through an open-drain or open-collector drive circuit, or through}
a 2.7-kΩ resistor in series with a totem pole drive circuit. If RS is left undriven, then a 20-kΩ pullup resistor should be used.
Figure 30. Reset Timings
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