SMJ320F240 Datasheet, PDF (59/99 Pages) Texas Instruments – DSP CONTROLLER

PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
50 Ω
CT
Output
Under
Test
SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
IOH
Where:
signal transition levels
IOL
=
IOH
=
VLOAD =
CT
=
2 mA (all outputs)
300 µA (all outputs)
1.5 V
110-pF typical load-circuit capacitance
Figure 16. Test Load Circuit
TTL-output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.7 V.
Figure 17 shows the TTL-level outputs.
2.4 V
80%
20%
0.7 V
Figure 17. TTL-Level Outputs
TTL-compatible output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower, and the level at which the output is said to be low is 20% of the total voltage
range and lower.
D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher, and the level at which the output is said to be high is 80% of the total voltage range and
higher.
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