SMJ320F240 Datasheet, PDF (39/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
general-purpose (GP) timers (continued)
DSP core
Data bus ADDR bus RESET INT2, 3, 4
SGUS029 – APRIL 1999
16
16
3
16
EV Control Registers
and Control Logic
Internal clock
16
GP timer 1 compare
16
16
GP Timer 1
16
16
16
16
Full Compare Units
16
GP Timer 2 Compare
2
TMRCLK
TMRDIR
ADC Start
Output
logic
T1PWM / T1CMP
3
SVPWM ₃
State
Machine
3
Output
Logic
PWM1 / CMP1
Dead
3
Output
Band
Units
Logic
PWM6 / CMP6
T2PWM / T2CMP
16
GP Timer 2
16
16
16
16
MUX
16
16
Simple Compare
3
Units
Output
Logic
16
GP Timer 3 Compare
16
GP Timer 3
16
16
MUX
16
16
Capture Units
Output
Logic
16
PWM7 / CMP7
PWM8 / CMP8
PWM9 / CMP9
T3PWM / T3CMP
To Control Logic
Dir
Clock
QEP
Circuit
2
2
2
CAP1 / QEP1
CAP2 / QEP2
CAP3, 4
Figure 11. Event-Manager Block Diagram
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39