SMJ320F240 Datasheet, PDF (22/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
hardware-generated interrupts (continued)
Each of the interrupt sources has its own control register with a flag bit and an enable bit. When an interrupt
request is received, the flag bit in the corresponding control register is set. If the enable bit is also set, a signal
is sent to arbitration logic, which can simultaneously receive similar signals from one or more of the other control
registers. The arbitration logic compares the priority level of competing interrupt requests, and it passes the
interrupt of highest priority to the CPU. The corresponding flag is set in the interrupt flag register (IFR), indicating
that the interrupt is pending. The CPU then must decide whether to acknowledge the request. Maskable
hardware interrupts are acknowledged only after certain conditions are met:
D Priority is highest. When more than one hardware interrupt is requested at the same time, the ’F240
services them according to the set priority ranking.
D INTM bit is 0. The interrupt mode (INTM) bit, bit 9 of status register ST0, enables or disables all maskable
interrupts:
– When INTM = 0, all unmasked interrupts are enabled.
– When INTM = 1, all unmasked interrupts are disabled.
INTM is set to 1 automatically when the CPU acknowledges an interrupt (except when initiated by the TRAP
instruction) and at reset. It can be set and cleared by software.
D IMR mask bit is 1. Each of the maskable interrupt lines has a mask bit in the interrupt mask register (IMR).
To unmask an interrupt line, set its IMR bit to 1.
When the CPU acknowledges a maskable hardware interrupt, it jams the instruction bus with the INTR
instruction. This instruction forces the PC to the appropriate address from which the CPU fetches the software
vector. This vector leads to an interrupt service routine.
Usually, the interrupt service routine reads the peripheral-vector-address offset from the peripheral-vector-
address register (see Table 7) to branch to code that is meant for the specific interrupt source that initiated the
interrupt request. The ’F240 includes a phantom-interrupt vector offset (0000h), which is a system interrupt
integrity feature that allows a controlled exit from an improper interrupt sequence. If the CPU acknowledges a
request from a peripheral when, in fact, no peripheral has requested an interrupt, the phantom-interrupt vector
is read from the interrupt-vector register.
Table 7 summarizes the interrupt sources, overall priority, vector address/offset, source, and function of each
interrupt available on the SMJ320F240.
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