SMJ320F240 Datasheet, PDF (6/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
BIT I/O AND SHARED FUNCTIONS PINS (CONTINUED)
T1PWM/T1CMP/
IOPB3
Bidirectional digital I/O. Timer 1 compare output. T1PWM/T1CMP/IOPB3 goes to the
105
I/O/Z high-impedance state when unmasked PDPINT goes active low. This pin is configured as a
digital input by all device resets.
T2PWM/T2CMP/
IOPB4
Bidirectional digital I/O. Timer 2 compare output. T2PWM/T2CMP/IOPB4 goes to the high-
106
I/O/Z impedance state when unmasked PDPINT goes active low. This pin is configured as a digital
input by all device resets.
T3PWM/T3CMP/
IOPB5
Bidirectional digital I/O. Timer 3 compare output. T3PWM/T3CMP/IOPB5 goes to the
107
I/O/Z high-impedance state when unmasked PDPINT goes active low. This pin is configured as a
digital input by all device resets.
TMRDIR/IOPB6
Bidirectional digital I/O. Direction signal for the timers. Up-counting direction if TMRDIR/IOPB6
108
I/O is low, down-counting direction if this pin is high.
This pin is configured as a digital input by all device resets.
TMRCLK/IOPB7
Bidirectional digital I/O.
109
I/O External clock input for general-purpose timers.
This pin is configured as a digital input by all device resets.
ADCSOC/IOPC0
Bidirectional digital I/O.
63
I/O External start of conversion input for ADC.
This pin is configured as a digital input by all device resets.
CAP1 / QEP1/IOPC4
67
Bidirectional digital I/O.
I/O Capture 1 or QEP 1 input.
This pin is configured as a digital input by all device resets.
CAP2 / QEP2/IOPC5
68
Bidirectional digital I/O.
I/O Capture 2 or QEP 2 input.
This pin is configured as a digital input by all device resets.
CAP3/IOPC6
Bidirectional digital I/O.
69
I/O Capture 3 input.
This pin is configured as a digital input by all device resets.
CAP4/IOPC7
Bidirectional digital I/O.
70
I/O Capture 4 input.
This pin is configured as a digital input by all device resets.
XF / IOPC2
Bidirectional digital I/O. External flag output (latched software-programmable signal). XF is
65
I/O used for signaling other processors in multiprocessing configurations or as a general-purpose
output pin. This pin is configured as an external flag output by all device resets.
BIO / IOPC3
Bidirectional digital I/O. Branch control input. BIO is polled by the BIOZ instruction. If BIO is low,
66
I/O the CPU executes a branch. If BIO is not used, it should be pulled high. This pin is configured
as a branch-control input by all device resets.
CLKOUT/IOPC1
Bidirectional digital I/O. Clock output. Clock output is selected by the CLKSRC bits in the
64
I/O
SYSCR register. This pin is configured as a DSP clock output by a power-on reset.
SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS
SCITXD/IO
44
I/O
SCI asynchronous serial port transmit data, or general-purpose bidirectional I/O. This pin is
configured as a digital input by all device resets.
SCIRXD/IO
43
I/O
† _{I = input, O = output, Z = high impedance}
SCI asynchronous serial port receive data, or general-purpose bidirectional I/O. This pin is
configured as a digital input by all device resets.
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