SMJ320F240 Datasheet, PDF (14/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
digital I/O and shared pin functions
The ’F240 has a total of 28 pins shared between primary functions and I/Os. These pins are divided into two
groups:
D Group1 — Primary functions shared with I/Os belonging to dedicated I/O ports, Port A, Port B, and Port C.
D Group2 — Primary functions belonging to peripheral modules which also have a built-in I/O feature as a
secondary function (for example, SCI, SPI, external interrupts, and PLL clock modules).
group1 shared I/O pins
The control structure for Group1 type shared I/O pins is shown in Figure 3. The only exception to this
configuration is the CLKOUT/IOPC1 pin. In Figure 3, each pin has three bits that define its operation:
D Mux control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
D I/O direction bit — if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
D I/O data bit — if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
IOP DIR Bit
0 = Input
1 = Output
IOP Data Bit
(Read/Write)
In
Out
Primary
Function
Note: When the MUX control bit = 1, the primary
function is selected in all cases except
for the following pins:
1. XF/IOPC2 (0 = Primary Function)
2. BIO/IOPC3 (0 = Primary Function)
0
1
MUX Control Bit
0 = I/O Function
1 = Primary Function
Primary
Function ^Pin
or I/O Pin
Figure 3. Shared Pin Configuration
A summary of Group1 pin configurations and associated bits is shown in Table 2.
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