SMJ320F240 Datasheet, PDF (49/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
scan-based emulation
SMJ320F240 devices use scan-based emulation for code- and hardware-development support. Serial scan
interface is provided by the test-access port. Scan-based emulation allows the emulator to control the processor
in the system without the use of intrusive cables to the full pinout of the device.
SMJ320F240 instruction set
The ’F240 microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upwardly compatible with the ’x2xx devices.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The SMJ320F240 instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.
In direct addressing, the instruction word contains the lower 7 bits of the data memory address. This field is
concatenated with the 9 bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, each page
containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0– AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or
subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing [used in fast fourier transforms (FFTs)] with increment or decrement. All operations are performed
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary
register and ARP can be modified.
In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There
are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained
in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the
second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need
to be stored or used more than once during the course of program execution (for example, initialization values
or constants).
The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference
to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,
operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand
address or immediate value.
repeat feature
The repeat function can be used with instructions (as defined in Table 14) such as multiply/accumulates (MAC
and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT ), and table read/writes (TBLR/TBLW).
These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they
effectively become single-cycle instructions. For example, the table-read instruction can take three or more
cycles to execute, but when the instruction is repeated, a table location can be read every cycle.
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