HD64F3337YCP16V Datasheet, PDF (689/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
7
6
5
4
CMFB CMFA OVF
—
0
0
0
1
R/(W)^*2 R/(W)^*2 R/(W)^*2 —
H'C9
TMR0
3
OS3 ^*1
0
R/W
2
OS2 ^*1
0
R/W
1
OS1^*1
0
R/W
0
OS0^*1
0
R/W
Output Select
0 0 No change on compare-match A.
0 1 Output 0 on compare-match A.
1 0 Output 1 on compare-match A.
1 1 Invert (toggle) output on compare-match A.
Output Select
0 0 No change on compare-match B.
0 1 Output 0 on compare-match B.
1 0 Output 1 on compare-match B.
1 1 Invert (toggle) output on compare-match B.
Timer Overflow Flag
0 Cleared by reading OVF = 1, then writing 0 in OVF.
1 Set when TCNT changes from H'FF to H'00.
Compare-Match Flag A
0 Cleared by reading CMFA = 1, then writing 0 in CMFA.
1 Set when TCNT = TCORA.
Compare-Match Flag B
0 Cleared by reading CMFB = 1, then writing 0 in CMFB.
1 Set when TCNT = TCORB.
Notes: *1 When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
*2 Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
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