HD64F3337YCP16V Datasheet, PDF (598/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Condition C Condition B
10 MHz
12 MHz
Item
Symbol Min Max Min Max
Ports Output data delay t_PWD
time
— 150 — 100
Input data setup
t_PRS
time
80 —
50 —
Input data hold time t_PRH
80 —
50 —
HIF
read
cycle
CS/HA₀ setup time
CS/HA₀ hold time
IOR pulse width
t_HAR
t_HRA
t_HRPW
10 —
10 —
220 —
10 —
10 —
120 —
HDB delay time
t_HRD
— 200 — 100
HDB hold time
t_HRF
0
40
0
25
HIRQ delay time
t_HIRQ
— 200 — 120
HIF
write
cycle
CS/HA₀ setup time
CS/HA₀ hold time
IOW pulse width
t_HAW
t_HWA
t_HWPW
10 —
10 —
100 —
10 —
10 —
60 —
High-speed GATE t_HDW
A₂₀ not uesd
50 —
30 —
High-speed GATE
A₂₀ uesd
85 —
55 —
HDB hold time
t_HWD
25 —
15 —
GA₂₀ delay time
t_HGA
— 180 — 90
Note: * In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V.
Condition A
16 MHz
Min Max Unit
— 100 ns
Test
Conditions
Fig. 23.21
50 — ns
50 — ns
10 — ns
10 — ns
120 — ns
— 100 ns
0
25 ns
— 120 ns
10 — ns
10 — ns
60 — ns
30 — ns
Fig. 23.22
Fig. 23.23
45 —
15 — ns
— 90 ns
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