HD64F3337YCP16V Datasheet, PDF (106/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7),
the program counter and condition code register might not be saved correctly, leading to a
program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a
reset. The first program instruction is therefore always executed. This instruction should initialize
the stack pointer (example: MOV.W #xx:16, SP).
After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation
instruction can be executed before an instruction to initialize the stack pointer. Immediately after
execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the
next instruction to initialize the stack pointer.
4.3 Interrupts
4.3.1 Overview
The interrupt sources include nine external sources from 23 input pins (NMI, IRQ₀ to IRQ₇, and
KEYIN₀ to KEYIN₇), and 26 (H8/3337 Series) or 23 (H8/3397 Series) internal sources in the on-
chip supporting modules. Table 4.2 lists the interrupt sources in priority order and gives their
vector addresses. When two or more interrupts are requested, the interrupt with highest priority is
served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts except
NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than
NMI are not accepted.
• IRQ₀ to IRQ₇ can be sensed on the falling edge of the input signal, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the
rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not have
to determine what type of interrupt has occurred.
• IRQ₆ is multiplexed with 8 external sources (KEYIN₀ to KEYIN₇). KEYIN₀ to KEYIN₇ can be
masked individually by user software.
• The watchdog timer can generate either an NMI or overflow interrupt, depending on the needs
of the application. For details, see section 11, Watchdog Timer.
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