HD64F3337YCP16V Datasheet, PDF (308/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

In receiving, the SCI operates as follows.
1. If an external clock is selected, data is input in synchronization with the input clock. If clock
output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock
and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the
serial clock and input of data resume as soon as the ORER bit is cleared to 0.
2. Receive data is shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from
RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in
RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 12.10.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The
RDRF bit is not set to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the
SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR
is set to 1, the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the
ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and
generate an overrun error.
Figure 12.16 shows an example of SCI receive operation.
Serial clock
Serial data
RDRF
Bit 0 Bit 1
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
ORER
276
RXI
request
RXI interrupt
handler reads
data in RDR and
clears RDRF to 0
RXI
request
1 frame
Figure 12.16 Example of SCI Receive Operation
Overrun error,
ERI request