HD64F3337YCP16V Datasheet, PDF (259/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 2to 0— Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained
by dividing the system clock (ø).
The overflow interval is the time from when the watchdog timer counter begins counting from
H'00 until an overflow occurs. In interval timer mode, WOVF interrupts are requested at this
interval.
Bit 2:
CKS2
0
1
Bit 1:
CKS1
0
1
0
1
Bit 0:
CKS0
0
1
0
1
0
1
0
1
Description
ø_P/2
ø_P/32
ø_P/64
ø_P/128
ø_P/256
ø_P/512
ø_P/2048
ø_P/4096
Overflow Interval (ø_P = 10 MHz)
51.2 µs
(Initial value)
819.2 µs
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
11.2.3 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
XRST NMIEG HIE
1
0
0
R
R/W
R/W
0
RAME
1
R/W
Only bit 3 is described here. For details of other bits, see section 3.2., System Control Register
(SYSCR), and descriptions of the relevant modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input.
XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by an internal reset due
to watchdog timer overflow when the RST/NMI bit is 1.
Bit 3: XRST
0
1
Description
A reset is generated by an internal reset due to watchdog timer overflow
A reset is generated by external reset input
(Initial value)
227