HD64F3337YCP16V Datasheet, PDF (118/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.3.6 Interrupt Response Time
Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is
accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling
routines in on-chip ROM and the stack in on-chip RAM.
Table 4.4 Number of States before Interrupt Service
Number of States
No.
Reason for Wait
On-Chip Memory
External Memory
1
Interrupt priority decision
2^{* 3}
2^{* 3}
2
Wait for completion of current 1 to 13
instruction^*1
5 to 17^*2
3
Save PC and CCR
4
12^{* 2}
4
Fetch vector
2
6^{* 2}
5
Fetch instruction
4
12^{* 2}
6
Internal processing
4
4
Total
17 to 29
41 to 53 ^*2
Notes: *1 These values do not apply if the current instruction is EEPMOV.
*2 If wait states are inserted in external memory access, add the number of wait states.
*3 1 for internal interrupts.
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt
becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR
or MOV instruction, for example, and the interrupt is requested during execution of that
instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution
of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a
higher-priority interrupt is requested at the same time, however, the hardware exception-handling
sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to 0.
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