HD64F3337YCP16V Datasheet, PDF (132/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6.
Table 6.3 Clock Timing
V_CC = 2.7 to
5.5 V
Item
Symbol Min Max
Low pulse
t _EXL
width of external
clock input
40 —
High pulse
t _EXH
width of external
clock input
40 —
External clock t_EXr
rise time
— 10
External clock t_EXf
fall time
— 10
Clock pulse
t _CL
width low
0.3 0.7
0.4 0.6
Clock pulse
t _CH
width high
0.3 0.7
0.4 0.6
V_CC = 4.0 to
5.5 V
Min Max
30 —
30 —
— 10
— 10
0.3 0.7
0.4 0.6
0.3 0.7
0.4 0.6
V_CC = 5.0 V
±10%
Min Max
20 —
20 —
—5
—5
0.3 0.7
0.4 0.6
0.3 0.7
0.4 0.6
Unit Test Conditions
ns Figure 6.6
ns
ns
ns
t_cyc ø ≥ 5 MHz Figure
t_cyc ø < 5 MHz ^20-4
t_cyc ø ≥ 5 MHz
t_cyc ø < 5 MHz
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXt
Figure 6.6 External Clock Input Timing
Table 6.4 shows the external clock output settling delay time. Figure 6.7 shows the timing for the
external clock output settling delay time. The oscillator and duty correction circuit have the
function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output settling delay time (t_DEXT). As clock signal output is not
confirmed during the t_DEXT period, the reset signal should be driven low and the reset state
maintained during this time.
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