HD64F3337YCP16V Datasheet, PDF (599/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 23.11 I²C Bus Timing
Conditions: V_CC = 2.7 V to 5.5 V*, V_SS = 0 V, Ta = –20˚C to +75˚C, ø ≥ 5 MHz
Item
SCL clock
cycle time
SCL clock
high pulse
width
SCL clock
low pulse
width
SCL, SDA
rise time
Symbol
t _SCL
Min
12t _cyc
t _SCLH
3t _cyc
Rating
Typ Max Unit
—
—
ns
—
—
ns
t _SCLL
5t _cyc
—
—
ns
t _Sr
—
—
1000 ns
20 + 0.1C_b —
300
SCL, SDA
t _Sf
fall time
—
—
20 + 0.1C_b —
300 ns
300
SDA bus
t _BUF
5t _cyc
free time
—
—
ns
SCL start
t _STAH
3t _cyc
condition
hold time
—
—
ns
SCL resend t_STAS
3t _cyc
start condition
hold time
—
—
ns
SDA stop
t _STOS
3t _cyc
condition
setup time
—
—
ns
SDA data
setup time
t _SDAS
0.5t_cyc
—
—
ns
SDA data
t _SDAH
0
hold time
—
—
ns
SDA load
C_b
—
capacitance
—
400 pF
Note: * In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V.
Test Condition Note
Figure 23.24
Normal mode
100 kbit/s (max)
High-speed mode
400 kbit/s (max)
Normal mode
100 kbit/s (max)
High-speed mode
400 kbit/s (max)
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