HD64F3337YCP16V Datasheet, PDF (117/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Interrupt
accepted
Interrupt priority
decision. Wait for Instruction Internal
end of instruction. prefetch process-
ing
Interrupt request
signal
Stack
Vector
fetch
Instruction prefetch
(first instruction of
Internal interrupt-handling
process- routine)
ing
ø
Internal address
(1)
(3)
(5)
(6)
(8)
(9)
bus
Internal read
signal
Internal write
signal
Internal 16-bit
data bus
(2)
(4)
(1)
(7)
(9)
(10)
(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling
routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
Figure 4.7 Timing of Interrupt Sequence
85