HD64F3337YCP16V Datasheet, PDF (538/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

21.2.2 Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
ESU
PSU
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
R/W
R/W
Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed.
FLMCR2 is an 8-bit register used for monitoring of flash memory program/erase protection (error
protection) and flash memory program/erase mode setup. FLMCR2 is initialized to H'00 by a reset
and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode,
hardware protect mode, and software protect mode.
When on-chip flash memory is disabled, a read will return H'00.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7: FLER
0
1
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing conditions]
Reset, hardware standby mode, subactive mode, subsleep mode, watch mode
(Initial value)
An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See Error Protection in section 21.4.5
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
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