HD64F3337YCP16V Datasheet, PDF (239/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
9.6.1 Contention between TCNT Write and Clear
If an internal counter clear signal is generated during the T₃ state of a write cycle to the timer
counter, the clear signal takes priority and the write is not performed.
Figure 9.10 shows this type of contention.
Write cycle: CPU writes to TCNT
T₁
T₂
T₃
ø
Internal address
bus
Internal write
signal
Counter clear
signal
TCNT address
TCNT
N
H'00
Figure 9.10 TCNT Write-Clear Contention
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