HD64F3337YCP16V Datasheet, PDF (318/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 0—Format Select (FS): Selects whether to use the addressing format or non-addressing
format in slave mode. The addressing format is used to recognize slave addresses.
Bit 0: FS
0
1
Description
Addressing format, slave addresses recognized
Non-addressing format
(Initial value)
13.2.3 I²C Bus Mode Register (ICMR)
Bit
7
6
5
4
3
2
1
0
MLS WAIT
—
—
—
BC2
BC1
BC0
Initial value
0
0
1
1
1
0
0
0
Read/Write R/W
R/W
—
—
—
R/W
R/W
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs wait control, and selects the transfer bit count. ICMR is assigned to the same
address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'38 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
Bit 7: MLS
0
1
Description
MSB-first
LSB-first
(Initial value)
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
and the acknowledge bit, in acknowledgement mode. When WAIT is set to 1, after the fall of the
clock for the final data bit, a wait state begins (with SCL staying at the low level). When bit IRIC
is cleared in ICSR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0,
data and acknowledge bits are transferred consecutively with no wait inserted.
Bit 6: WAIT
0
1
Description
Data and acknowledge transferred consecutively
Wait inserted between data and acknowledge
(Initial value)
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