HD64F3337YCP16V Datasheet, PDF (278/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.2.8 Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit
rate output by the baud rate generator.
BRR is initialized to H'FF by a reset and in the standby modes.
Tables 12.3 and 12.6 show examples of BRR settings.
Table 12.3 Examples of BRR Settings in Asynchronous Mode (When ø_P = ø)
Bit Rate
(bits/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
ø (MHz)
2
2.097152
nN
Error
(%)
nN
Error
(%)
1 141 +0.03 1 148 –0.04
1 103 +0.16 1 108 +0.21
0 207 +0.16 0 217 +0.21
0 103 +0.16 0 108 +0.21
0 51 +0.16 0 54 –0.70
0 25 +0.16 0 26 +1.14
0 12 +0.16 0 13 –2.48
—— —
0 6 –2.48
—— —
—— —
01 0
—— —
—— —
—— —
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