HD64F3337YCP16V Datasheet, PDF (613/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 23.22 Timing Conditions of On-Chip Supporting Modules
Conditions: V_CC = 3.0 V to 5.5 V, V_SS = 0 V, ø = 2.0 MHz to maximum operating frequency,
Ta = –20˚C to +75˚C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition
10 MHz
Item
Symbol Min
Max
Unit Test Conditions
FRT
TMR
Timer output delay time
t_FTOD
—
Timer input setup time
t_FTIS
80
Timer clock input setup time
t_FTCS
80
Timer clock pulse width
t_FTCWH
1.5
t_FTCWL
Timer output delay time
t_TMOD
—
Timer reset input setup time
t_TMRS
80
Timer clock input setup time
t_TMCS
80
Timer clock pulse width (single t_TMCWH
1.5
edge)
150
ns
Fig. 23.13
—
ns
—
ns
Fig. 23.14
—
t_cyc
150
ns
Fig. 23.15
—
ns
Fig. 23.17
—
ns
Fig. 23.16
—
t_cyc
Timer clock pulse width (both
t_TMCWL
2.5
—
t_cyc
edges)
PWM
SCI
Timer output delay time
t_PWOD
—
Input clock cycle (Async)
t_Scyc
4
(Sync)
6
150
ns
Fig. 23.18
—
t_cyc
Fig. 23.19
—
t_cyc
Transmit data delay time (Sync) t_TXD
—
200
ns
Receive data setup time (Sync) t_RXS
150
—
ns
Receive data hold time (Sync) t_RXH
150
—
ns
Input clock pulse width
t_SCKW
0.4
0.6
t_Scyc Fig. 23.20
Ports
Output data delay time
t_PWD
—
150
ns
Fig. 23.21
Input data setup time
t_PRS
80
—
ns
Input data hold time
t_PRH
80
—
ns
HIF read
cycle
CS/HA₀ setup time
CS/HA₀ hold time
t_HAR
10
—
ns
Fig. 23.22
t_HRA
10
—
ns
IOR pulse width
t_HRPW
220
—
ns
HDB delay time
t_HRD
—
200
ns
HDB hold time
t_HRF
0
40
ns
HIRQ delay time
t_HIRQ
—
200
ns
HIF write
cycle
CS/HA₀ setup time
CS/HA₀ hold time
t_HAW
10
—
ns
Fig. 23.23
t_HWA
10
—
ns
IOW pulse width
t_HWPW
100
—
ns
High-speed GATE A₂₀ not uesd t_HDW
50
—
ns
High-speed GATE A₂₀ uesd
85
—
HDB hold time
t_HWD
25
—
ns
GA₂₀ delay time
t_HGA
—
180
ns
581