HD64F3337YCP16V Datasheet, PDF (350/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14.1.3 Register Configuration
Table 14.2 lists the host interface registers.
Table 14.2 HIF Registers
R/W
Name
Abbreviation Slave Host
System control register SYSCR
R/W^*1 —
Initial
Value
H'09
Slave
Master Address^*4
Address^*3 CS₁ CS₂ HA₀
H'FFC4 — — —
Host interface control HICR
register
R/W —
H'F8 H'FFF0 — — —
Input data register 1 IDR1
R
W
—
H'FFF4 0
1
0/1^*5
Output data register 1 ODR1
R/W R
—
H'FFF5 0 1 0
Status register 1
STR1
R/(W)^*2 R
H'00 H'FFF6 0 1 1
Input data register 2 IDR2
R
W
—
H'FFFC 1
0
0/1^*5
Output data register 2 ODR2
R/W R
—
H'FFFD 1 0 0
Status register 2
STR2
R/(W)^*2 R
H'00 H'FFFE 1 0 1
Serial/timer control
register
STCR
R/W —
H'00 H'FFC3 — — —
Notes: *1 Bit 3 is a read-only bit.
*2 The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
*3 Address when accessed from the slave processor.
*4 Pin inputs used in access from the host processor.
*5 The HA₀ input discriminates between writing of commands and data.
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