HD64F3337YCP16V Datasheet, PDF (137/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 6.8 External Clock Output Stabilization Delay Time
Conditions: V_CC = 3.0 to 5.5 V, AV_CC = 2.7 to 5.5 V, V_SS = AV_SS = 0 V
Item
Symbol
Min
External clock output stabilization
t * _DEXT
500
delay time
Note: * t_DEXT includes a 10 t_cyc RES pulse width (t_RESW).
Max
—
Unit
µs
Notes
Figure 6.13
V_CC 3.0 V
STBY
V_IH
EXTAL
ø (internal and
external)
RES
t_DEXT*
Note: * t_DEXT includes a 10 t_cyc RES pulse width (t_RESW).
Figure 6.13 External Clock Output Stabilization Delay Time
6.3 Duty Adjustment Circuit
When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of
the signal from the oscillator circuit to generate the system clock (ø).
6.4 Prescaler
The clock for the on-chip supporting modules (ø_P) has either the same frequency as the system
clock (ø) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides
the frequency of ø_P to generate internal clock signals with frequencies from ø_P/2 to ø_P/4096.
105