HD64F3337YCP16V Datasheet, PDF (670/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCR—Timer Control Register
H'96
FRT
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock Select
0 0 Internal clock source: ø_P/2
0 1 Internal clock source: ø_P/8
1 0 Internal clock source: ø_P/32
1 1 External clock source: counted on rising edge
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
638