HD64F3337YCP16V Datasheet, PDF (202/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2: BUFEB
0
1
Description
ICRD is used for input capture D.
ICRD is used as a buffer register for input capture B.
(Initial value)
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for FRC. External clock pulses are counted on the rising edge of
signals input to pin FTCI.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
ø_P/2 internal clock source
ø_P/8 internal clock source
ø_P/32 internal clock source
External clock source (rising edge)
(Initial value)
8.2.7 Timer Output Compare Control Register (TOCR)
Bit
7
6
5
4
3
—
—
—
OCRS OEA
Initial value
1
1
1
0
0
Read/Write
—
—
—
R/W
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
0
OLVLB
0
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, and switches access between output compare registers A and B.
TOCR is initialized to H'E0 by a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4: OCRS
0
1
Description
OCRA is selected.
OCRB is selected.
(Initial value)
170