HD64F3337YCP16V Datasheet, PDF (427/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Sample Program for Programming One Byte: This program uses the following registers.
R0H: Specifies blocks to be erased.
R1H: Stores data to be programmed.
R1L: Stores data to be read.
R3: Stores address to be programmed. Valid addresses are H'0000 to H'7FFF.
R4: Sets program and program-verify timing loop counters, and also stores register setting
value.
R5: Sets program timing loop counter.
R6L: Used for program-verify fail count.
Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data
in R1H.
The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to
tables 19.9 (1) and (2).
FLMCR:
EBR1:
EBR2:
TCSR:
.EQU
.EQU
.EQU
.EQU
H'FF80
H'FF82
H'FF83
H'FFA8
PRGM:
PRGMS:
LOOP1:
LOOP2:
.ALIGN
MOV.B
MOV.B
MOV.B
MOV.W
MOV.B
INC
MOV.W
MOV.W
MOV.W
BSET
SUBS
MOV.W
BNE
BCLR
MOV.W
MOV.W
MOV.B
BSET
DEC
BNE
MOV.B
CMP.B
BEQ
BCLR
2
#H'**,
R0H,
R0H ;
@EBR*:8 ;
Set EBR*
#H'00, R6L
; Program-verify fail counter
#H'a, R5
; Set program loop counter
R1H,
@R3
; Dummy write
R6L
; Program-verify fail counter + 1 → R6L
#H'A578, R4
;
R4,
@TCSR ; Start watchdog timer
R5,
R4
; Set program loop counter
#0,
@FLMCR:8 ;
Set P bit
#1,
R4
;
R4,
R4
;
LOOP1
; Wait loop
#0,
@FLMCR:8 ;
Clear P bit
#H'A500, R4
;
R4,
@TCSR ; Stop watchdog timer
#H'b ,
#2,
R4H
LOOP2
@R3,
R1H,
PVOK
#2,
R4H
; Set program-verify loop counter
@FLMCR:8 ;
Set PV bit
;
; Wait loop
R1L
; Read programmed address
R1L
; Compare programmed data with read data
; Program-verify decision
@FLMCR:8 ;
Clear PV bit
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