HD64F3337YCP16V Datasheet, PDF (257/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count
overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1.
TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.
Note: TCNT is write-protected by a password. See Section 11.2.3, Register Access, for details.
11.2.2 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
3
2
1
— RST/NMI CKS2 CKS1
1
0
0
0
—
R/W
R/W
R/W
Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
0
CKS0
0
R/W
TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and
performs other functions.
Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are
initialized to 0 by a reset, but retain their values in the standby modes.
Note: TCSR is write-protected by a password. See section 11.2.3, Register Access, for details.
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