HD64F3337YCP16V Datasheet, PDF (209/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8.4.2 Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8.6 shows the
timing of this operation for compare-match A.
ø
FRC
N
N+1
N
N+1
OCRA
N
Internal compare-
match A signal
OLVLA
N
Clear*
FTOA
Note: * Cleared by software
Figure 8.6 Timing of Output Compare A
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