HD64F3337YCP16V Datasheet, PDF (572/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22.1.1 System Control Register (SYSCR)
Four of the eight bits in the system control register (SYSCR) control the power-down state. These
are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 22.2.
Table 22.2 System Control Register
Name
System control register
Abbreviation
R/W
SYSCR
R/W
Initial Value
H'09
Address
H'FFC4
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
3
2
1
STS0 XRST NMIEG HIE
0
1
0
0
R/W
R
R/W
R/W
0
RAME
1
R/W
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to software standby
mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to 1. To
clear this bit, software must write a 0.
Bit 7: SSBY
0
1
Description
The SLEEP instruction causes a transition to sleep mode.
(Initial value)
The SLEEP instruction causes a transition to software standby mode.
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