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HD64F3337YCP16V Datasheet, PDF (489/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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20.4.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Start
Set erase block register
(set bit of block to be erased to 1)
Write 0 data in all addresses
to be erased (prewrite)*1
n=1
Enable watchdog timer*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms*5
Clear E bit
Disable watchdog timer
Set top address in block
as verify address
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs*6
Dummy write to verify address*3
(flash memory latches address)
Notes: *1 Program all addresses to be erased
by following the prewrite flowchart.
*2 Set the watchdog timer overflow
interval to the value indicated in
table 20.8.
*3 For the erase-verify dummy write,
write H'FF with a byte transfer
Erasing ends
instruction.
*4 Read the data to be verified with a
byte transfer instruction. When
erasing two or more blocks, clear
the bits of erased blocks in the
erase block registers, so that only
unerased blocks will be erased
again.
*5 The erase time x is successively
incremented by the initial set value
à 2nâ1 (n = 1, 2, 3, 4). An initial
value of 6.25 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
*6 tVS1: 4 µs or more
tVS2: 2 µs or more
N: 602
Wait (tVS2) µs*6
Address + 1 â address
Verify*4 (read data=H'FF?)
OK
No
Last address?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
No go
End of block erase
Clear EV bit
n ⥠N?*6
Yes
Erase error
Erase-verify ends
No
n+1ân
Yes
n > 4?
No
Double erase time
(x à 2âx)
Figure 20.9 Erasing Flowchart
457
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