HD64F3337YCP16V Datasheet, PDF (345/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

SCL
SDA
SCL high level duration maintained
VIH
SCL low level detected
IRIC
SCL determined to be low level
IRIC cleared
Figure 13.20 IRIC Flag Clear Timing when WAIT = 1
Note that the clock may not be output properly during the next master send if receive data
(ICDR data) is read during the time between when the instruction to issue a stop condition is
executed (writing 0 to BBSY and SCP in ISSR) and when the stop condition is actually
generated.
In addition, overwriting of IIC control bits in order to change the send or receive operation
mode or to change settings, such as for example clearing the MST bit after completion of
master send or receive, should always be performed during the period indicated as (a) in Figure
13.21 below (after confirming that the BBSY bit in the ICCR register has been cleared to 0).
SDA
SCL
Internal clock
BBSY bit
Bit 0
A
8
9
Stop condition
(a)
Master receive mode
ICDR read F
prohibited duration
Start condition
Execution of issue
Stop condition generated
stop condition instruction
(BBSY = 0 read)
(BBSY = 0 and SCP = 0 written)
Start condition issued
Figure 13.21 Precautions when Reading Master Receive Data
313