HD64F3337YCP16V Datasheet, PDF (326/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13.2.6 Serial/Timer Control Register (STCR)
Bit
7
6
5
4
IICS
IICD
IICX
IICE
Initial value
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
3
STAC
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
0
ICKS0
0
R/W
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset and in hardware
standby mode.
Bit 7—I²C Extra Buffer Select (IICS): This bit is reserved, but it can be written and read. Its
initial value is 0.
Bit 6—I²C Extra Buffer Reserve (IICD): This bit is reserved, but it can be written and read. Its
initial value is 0.
Bit 5—I²C Transfer Rate Select (IICX): This bit, in combination with bits CKS2 to CKS0 in
ICCR, selects the transfer rate in master mode. For details regarding transfer rate, refer to section
13.2.4, I²C Bus Control Register (ICCR).
Bit 4—I²C Master Enable (IICE): Controls CPU access to the data and control registers (ICCR,
ICSR, ICDR, ICMR/SAR) of the I²C bus interface.
Bit 4: IICE
0
1
Description
CPU access to I²C bus interface data and control registers is disabled
(Initial value)
CPU access to I²C bus interface data and control registers is enabled
Bit 3—Slave Input Switch (STAC): Switches host interface input pins. For details, see section
14, Host Interface.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1. For details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit
Timers.
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