HD64F3337YCP16V Datasheet, PDF (576/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22.3.3 Clock Settling Time for Exit from Software Standby Mode
Set bits STS2 to STS0 in SYSCR as follows:
• Crystal oscillator
Set STS2 to STS0 for a settling time of at least 8 ms. Table 22.3 lists the settling times selected
by these bits at several clock frequencies.
• External clock
The STS bits can be set to any value. The shortest time setting (STS2=STS1=STS0=0) is
recommended in most cases. When 1,024 states (STS2 to STS0 = 101) is selected, the
following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when
1,024 states is specified for the setting time. To avoid this problem, set the STS value just
before the transition to software standby mode (before executing the SLEEP instruction), and
re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby
mode is cleared by an interrupt.
Table 22.3 Times Set by Standby Timer Select Bits (Unit: ms)
Settling
Time
System Clock Frequency (MHz)
STS2 STS1 STS0 (States) 16 12 10 8
6
4
2
1
0.5
0
0
0
8,192 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 16.4
0
0
1
16,384 1.0 1.3 1.6 2.0 2.7 4.1 8.2 16.4 32.8
0
1
0
32,768 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8 65.5
0
1
1
65,536 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5 131.1
1
0
0/—* 131,072 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1 262.1
Note: Recommended values are printed in boldface.
* F-ZTAT version/ZTAT and mask-ROM versions.
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