HD64F3337YCP16V Datasheet, PDF (256/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11.1.2 Block Diagram
Figure 11.1 is a block diagram of the watchdog timer.
Internal reset or
internal NMI
(Watchdog timer mode)
WOVF interrupt
request signal
(Interval timer mode)
Interrupt
control
TCNT: Timer counter
TCSR: Timer control/status register
Overflow
Clock
TCNT
TCSR
Read/write
control
Internal
data bus
Internal clock source
Clock
select
ø_P/2
ø_P/32
ø_P/64
ø_P/128
ø_P/256
ø_P/512
ø_P/2048
ø_P/4096
Figure 11.1 Block Diagram of Watchdog Timer
11.1.3 Register Configuration
Table 11.1 lists information on the watchdog timer registers.
Table 11.1 Register Configuration
Name
Abbreviation R/W
Initial
Value
Addresses
Write
Read
Timer control/status register
TCSR
R/(W)* H'10
H'FFA8 H'FFA8
Timer counter
TCNT
R/W
H'00
H'FFA8 H'FFA9
Note: * Software can write a 0 to clear the status flag bits, but cannot write 1.
224