HD64F3337YCP16V Datasheet, PDF (266/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

• Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested
independently.
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of one serial communication interface channel.
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
TSR
Parity
generate
Parity check
SSR
SCR
SMR
Communi-
cation
control
BRR
Baud rate
generator
Clock
Internal
clock
ø
ø_P/4
ø_P/16
ø_P/64
External clock source
RSR: Receive shift register (8 bits)
RDR: Receive data register (8 bits)
TSR: Transmit shift register (8 bits)
TDR: Transmit data register (8 bits)
SMR: Serial mode register (8 bits)
SCR: Serial control register (8 bits)
SSR: Serial status register (8 bits)
BRR: Bit rate register (8 bits)
TEI
TXI
RXI
ERI
Interrupt signals
Figure 12.1 Block Diagram of Serial Communication Interface
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