HD64F3337YCP16V Datasheet, PDF (379/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol Min Typ Max
Min Typ Max
Synchronization delay
t_D
10
—
17
6
—
9
Input sampling time*
t _SPL
—
80
—
—
40
—
A/D conversion time*
t _CONV
259 —
266
131 —
134
Note: * Values in the table are numbers of states. Values are for øP = ø. When øP = ø/2, the
values are doubled.
15.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the
timing.
ø
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 15.6 External Trigger Input Timing
347