HD64F3337YCP16V Datasheet, PDF (600/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 23.12 External clock output delay Timing
Conditions: V_CC = 2.7 V to 5.5 V^*2, AV_CC = 2.7 V to 5.5 V^*2,
V_SS = AV_SS = 0V, Ta = –40˚C to +85˚C
Item
Symbol Min
Max Unit Notes
External clock output delay time
t *1
DEXT
500
—
µs
Figure 23.25
Notes: *1 t_DEXT includes to RES pulse width t_RESW (10 tcyc).
*2 In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V.
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