HD64F3337YCP16V Datasheet, PDF (241/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.6.3 Contention between TCOR Write and Compare-Match
If a compare-match occurs during the T₃ state of a write cycle to TCOR, the write takes priority
and the compare-match signal is inhibited.
Figure 9.12 shows this type of contention.
Write cycle: CPU writes to TCOR
T₁
T₂
T₃
ø
Internal address bus
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare-match
A or B signal
Inhibited
Figure 9.12 Contention between TCOR Write and Compare-Match
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