HD64F3337YCP16V Datasheet, PDF (250/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal
clock sources obtained by dividing the supporting-module clock (ø_P).
Bit 2: CKS2
0
1
Bit 1: CKS1
0
1
0
1
Bit 0: CKS0
0
1
0
1
0
1
0
1
Description
ø_P/2
ø_P/8
ø_P/32
ø_P/128
ø_P/256
ø_P/1024
ø_P/2048
ø_P/4096
(Initial value)
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution × 250
PWM frequency = 1/PWM period
If the ø_P clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM output
for each clock source are as shown in table 10.3.
Table 10.3 PWM Timer Parameters for 10 MHz System Clock
Internal Clock Frequency
ø_P/2
ø_P/8
ø_P/32
ø_P/128
ø_P/256
ø_P/1024
ø_P/2048
ø_P/4096
Resolution
200 ns
800 ns
3.2 µs
12.8 µs
25.6 µs
102.4 µs
204.8 µs
409.6 µs
PWM Period
50 µs
200 µs
800 µs
3.2 ms
6.4 ms
25.6 ms
51.2 ms
102.4 ms
PWM Frequency
20 kHz
5 kHz
1.25 kHz
312.5 Hz
156.3 Hz
39.1 Hz
19.5 Hz
9.8 Hz
218