HD64F3337YCP16V Datasheet, PDF (668/749 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCSR—Timer Control/Status Register
H'91
FRT
Bit
Initial value
Read/Write
7
ICFA
0
R/(W) *
6
ICFB
0
R/(W) *
5
ICFC
0
R/(W) *
4
3
ICFD OCFA
0
0
R/(W) * R/(W) *
2
OCFB
0
R/(W) *
1
0
OVF CCLRA
0
0
R/(W)* R/W
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
Timer Overflow Flag
0 Cleared by reading OVF = 1, then writing 0 in OVF.
1 Set when FRC changes from H'FFFF to H'0000.
Output Compare Flag B
0 Cleared by reading OCFB = 1, then writing 0 in OCFB.
1 Set when FRC = OCRB.
Output Compare Flag A
0 Cleared by reading OCFA = 1, then writing 0 in OCFA.
1 Set when FRC = OCRA.
Input Capture Flag D
0 Cleared by reading ICFD = 1, then writing 0 in ICFD.
1 Set when an input capture signal is received.
Input Capture Flag C
0 Cleared by reading ICFC = 1, then writing 0 in ICFC.
1 Set when an input capture signal is received.
Input Capture Flag B
0 Cleared by reading ICFB = 1, then writing 0 in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0 Cleared by reading ICFA = 1, then writing 0 in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
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